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19-2827; Rev 0; 4/03
670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters
General Description
The MAX9174/MAX9175 are 670MHz, low-jitter, lowskew 1:2 splitters ideal for protection switching, loopback, and clock and signal distribution. The devices feature ultra-low 1.0ps(RMS) random jitter (max) that ensures reliable operation in high-speed links that are highly sensitive to timing errors. The MAX9174 has a fail-safe LVDS input and LVDS outputs. The MAX9175 has an anything differential input (CML/LVDS/LVPECL) and LVDS outputs. The outputs can be put into high impedance using the power-down inputs. The MAX9174 features a fail-safe circuit that drives the outputs high when the input is open, undriven and shorted, or undriven and terminated. The MAX9175 has a bias circuit that forces the outputs high when the input is open. The power-down inputs are compatible with standard LVTTL/LVCMOS logic. The power-down inputs tolerate undershoot of -1V and overshoot of VCC + 1V. The MAX9174/MAX9175 are available in 10-pin MAX and 10-lead thin QFN with exposed pad packages, and operate from a single +3.3V supply over the -40C to +85C temperature range. o 1.0ps(RMS) Jitter (max) at 670MHz o 80ps(P-P) Jitter (max) at 800Mbps Data Rate o +3.3V Supply o LVDS Fail-Safe Inputs (MAX9174) o Anything Input (MAX9175) Accepts Differential CML/LVDS/LVPECL o Power-Down Inputs Tolerate -1.0V and VCC + 1.0V o Low-Power CMOS Design o 10-Lead MAX and Thin QFN Packages o -40C to +85C Operating Temperature Range o Conform to ANSI TIA/EIA-644 LVDS Standard o IEC 61000-4-2 Level 4 ESD Rating
Features
MAX9174/MAX9175
Ordering Information
PART MAX9174EUB MAX9174ETB* MAX9175EUB MAX9175ETB* TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 10 MAX 10 Thin QFN-EP** 10 MAX 10 Thin QFN-EP**
Applications
Protection Switching Loopback Clock Distribution
Functional Diagram and Pin Configurations appear at end of data sheet.
*Future product--contact factory for availability. **EP = Exposed paddle.
Typical Application Circuit
CLOCK DISTRIBUTION ASIC MAX9174 MAX9176
CLK IN CLK1
ASIC MAX9174 MAX9176
CLK IN CLK2
________________________________________________________________ Maxim Integrated Products
1
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670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters MAX9174/MAX9175
ABSOLUTE MAXIMUM RATINGS
VCC to GND ..................................................-0.3V to +4.0V IN+, IN- to GND....................................................-0.3V to +4.0V OUT_+, OUT_- to GND..........................................-0.3V to +4.0V PD0, PD1 to GND .......................................-1.4V to (VCC + 1.4V) Single-Ended and Differential Output Short-Circuit Duration (OUT_+, OUT_-) .....................Continuous Continuous Power Dissipation (TA = +70C) 10-Pin MAX (derate 5.6mW/C above +70C) ...........444mW 10-Lead QFN (derate 24.4mW/C above +70C) ......1951mW Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection Human Body Model (RD = 1.5k, CS = 100pF) IN+, IN-, OUT_+, OUT_-..................................................2kV Other Pins (VCC, PD0, PD1) ...............................................2kV IEC 61000-4-2 Level 4 (RD = 330, CS = 150pF) Contact Discharge IN+, IN-, OUT_+, OUT_- ...................8kV Air-Gap Discharge IN+, IN-, OUT_+, OUT_- .................15kV Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 100 1%, PD_ = high, differential input voltage |VID| = 0.05V to 1.2V, MAX9174 input common-mode voltage VCM = |VID /2| to (2.4V - |VID /2|), MAX9175 input common-mode voltage VCM = |VID /2| to (VCC - | VID /2|), TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, |VID| = 0.2V, VCM = +1.25V, TA = +25C.) (Notes 1, 2, 3)
PARAMETER DIFFERENTIAL INPUT (IN+, IN-) Differential Input High Threshold Differential Input Low Threshold Input Current VTH VTL IIN+, IINIIN+, IINRIN1 RIN2 RIN3 Figure 1 MAX9174 Power-Off Input Current MAX9175 VCC = 0V or open, Figure 1 VIN+ = 3.6V or 0V, VIN- = 3.6V or 0V, VCC = 0V or open, Figure 1 -20 +20 A -50 -20 +20 +50 mV mV A SYMBOL CONDITIONS MIN TYP MAX UNITS
Fail-Safe Input Resistors (MAX9174) Input Resistors (MAX9175)
VCC = 3.6V, 0V or open, Figure 1 VCC = 3.6V, 0V or open, Figure 1 IN+ or IN- to GND (Note 4)
60 200 212
108 394 450 4.5 VCC + 1 +0.8 +20 +1.5
k k pF
Input Capacitance CIN P LVTTL/LVCMOS INPUTS (PD 0, PD 1) Input High Voltage Input Low Voltage Input Current LVDS OUTPUTS (OUT_+, OUT_-) Differential Output Voltage Change in Differential Output Voltage Between Logic States Offset Voltage VOD VOD VOS VIH VIL
2.0 -1.0 -1.0V PD_ 0V -1.5 -20 0V PD_ VCC VCC PD_ VCC + 1.0V Figure 2 Figure 2 Figure 3 1.125 250 393 1.0 1.29
V V mA A mA mV mV V
IIN
475 15 1.375
2
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670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, RL = 100 1%, PD_ = high, differential input voltage |VID| = 0.05V to 1.2V, MAX9174 input common-mode voltage VCM = |VID /2| to (2.4V - |VID /2|), MAX9175 input common-mode voltage VCM = |VID /2| to (VCC - | VID /2|), TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, |VID| = 0.2V, VCM = +1.25V, TA = +25C.) (Notes 1, 2, 3)
PARAMETER Change in Offset Voltage Between Logic States Fail-Safe Differential Output Voltage (MAX9174) Differential Output Resistance Power-Down Single-Ended Output Current SYMBOL VOS VOD RDIFF Figure 3 Figure 2 VCC = 3.6V or 0V VOUT_+ = open, VOUT_- = 3.6V or 0V VOUT_- = open, VOUT_+ = 3.6V or 0V PD0, PD1 = low, VCC = 0V or open VOUT_+ = open, VOUT_- = 3.6V or 0V VOUT_- = open, VOUT_+ = 3.6V or 0V -15 250 86 CONDITIONS MIN TYP 1.0 393 119 MAX 15 475 160 UNITS mV mV
MAX9174/MAX9175
IPD
PD_ = low
-1.0
0.03
+1.0
A
Power-Off Single-Ended Output Current
IOFF
-1.0
0.03
+1.0
A
Output Short-Circuit Current Differential Output Short-Circuit Current Magnitude Supply Current Power-Down Supply Current Output Capacitance
IOS
VID = +50mV or -50mV, VOUT_+ = 0V or VCC VID = +50mV or -50mV, VOUT_- = 0V or VCC
+15
mA
IOSD
VID = +50mV or -50mV, VOD = 0V (Note 4) PD0 = VCC, PD1 = 0V or PD0 = 0V, PD1 = VCC PD0 = Vcc, PD1 = Vcc PD1, PD0 = 0V OUT_+ or OUT_- to GND (Note 4) 17 25 0.5
15 26 35 20 5.2
mA
ICC ICCPD CO
mA A pF
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670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters MAX9174/MAX9175
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, RL = 1001%, CL = 5pF, differential input voltage |VID| = 0.15V to 1.2V, MAX9174 input common-mode voltage, VCM = |VID/2| to (2.4V - |VID/2|), MAX9175 input common-mode voltage VCM = |VID/2| to (VCC - |VID/2|), PD_ = high, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, |VID| = 0.2V, VCM = +1.25V, TA = +25C.) (Notes 5, 6, 7)
PARAMETER High-to-Low Propagation Delay Low-to-High Propagation Delay Added Deterministic Jitter Added Random Jitter Pulse Skew tPLH - tPHL Output-to-Output Skew Part-to-Part Skew Rise Time Fall Time Power-Down Time Power-Up Time SYMBOL tPHL tPLH tDJ tRJ tSKP tSKOO tSKPP1 tSKPP2 tR tF tPD tPU Figures 4, 5 Figures 4, 5 Figures 4, 5 (Note 8) Figures 4, 5 Figures 4, 5 Figure 6 Figures 4, 5 (Note 9) Figures 4, 5 (Note 10) Figures 4, 5 Figures 4, 5 Figures 7, 8 PD0, PD1 = L H, Figures 7, 8 PD0 = H, PD1 = L H, Figures 7, 8 PD1 = H, PD0 L H, Figures 7, 8 Maximum Data Rate Maximum Switching Frequency Switching Supply Current PRBS Supply Current DRMAX fMAX ICCSW ICCPR Figures 4, 5, VOD 250mV (Note 11) Figures 4, 5, VOD 250mV (Note 11) fIN = 670MHz fIN = 155MHz DR = 800Mbps, 223 - 1 PRBS input 800 670 55 35 37 65 44 46 110 110 257 252 10 18 92 92 10 14 0.4 CONDITIONS MIN 1.33 1.33 TYP 2.38 2.39 MAX 3.23 3.23 80 1.0 141 45 1.3 1.9 365 365 13 35 103 103 UNITS ns ns ps(P-P) ps(RMS) ps ps ns ps ps ns s ns Mbps MHz mA mA
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH, VTL, VID, VOD, and VOD. Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are 100% tested at TA = +25C. Note 3: Tolerance on all external resistors (including figures) is 1%. Note 4: Guaranteed by design. Note 5: AC parameters are guaranteed by design and characterization and are not production tested. Limits are set at 6 sigma. Note 6: CL includes scope probe and test jig capacitance. Note 7: Pulse-generator output for differential inputs IN+, IN- (unless otherwise noted): f = 670MHz, 50% duty cycle, RO = 50, tR = 700ps, and tF = 700ps (0% to 100%). Pulse-generator output for single-ended inputs PD0, PD1: tR = tF = 1.5ns (0.2VCC to 0.8VCC), 50% duty cycle, VOH = VCC + 1.0V settling to VCC, VOL = -1.0V settling to zero, f = 10kHz. Note 8: Pulse-generator output for tDJ: |VOD| = 0.15V, VOS = 1.25V, data rate 800Mbps, 223 - 1 PRBS, RO = 50, tR = 700ps, and tF = 700ps (0% to 100%). Note 9: tSKPP1 is the magnitude of the difference of any differential propagation delays between devices operating under identical conditions. Note 10: tSKPP2 is the magnitude of the difference of any differential propagation delays between devices operating over rated conditions. Note 11: Meets all AC specifications.
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670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters
Typical Operating Characteristics
((MAX9174) VCC = +3.3V, |VID| = 0.15V, VCM = 1.25V, TA = +25C, RL = 100 1%, CL = 5pf, PD_ = VCC, unless otherwise noted.)
DIFFERENTIAL OUTPUT VOLTAGE vs. FREQUENCY
MAX9174 toc01 MAX9174 toc02
MAX9174/MAX9175
SUPPLY CURRENT vs. TEMPERATURE
38 fIN = 155MHz 37 SUPPLY CURRENT (mA) 36 35 34 33 32 -40 -15 10 35 60 85 TEMPERATURE (C) 410 DIFFERENTIAL OUTPUT VOLTAGE (mV) 400 390 380 370 360 350 340 330 320 310 300 0
OUTPUT RISE/FALL TIME vs. TEMPERATURE
290 280 RISE/FALL TIME (ps) 270 260 250 240 230 220 210 tF tR fIN = 155MHz
MAX9174 toc03
300
100 200 300 400 500 600 700 800 FREQUENCY (MHz)
-40
-15
10
35
60
85
TEMPERATURE (C)
DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE
MAX9174 toc04
OUTPUT-TO-OUTPUT SKEW vs. TEMPERATURE
MAX9174 toc05
SUPPLY CURRENT vs. FREQUENCY
55 SUPPLY CURRENT (mA) 50 45 40 35 30 25 20
MAX9174 toc06
3.0 DIFFERENTIAL PROPAGATION DELAY (ns) 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 -40 -15 10 35 60 tPLH tPHL fIN = 155MHz
20 18 OUTPUT-TO-OUTPUT SKEW (ps) 16 14 12 10 8 6 4 2 0 fIN = 155MHz
60
85
-40
-15
10
35
60
85
0
100 200 300 400 500 600 700 800 FREQUENCY (MHz)
TEMPERATURE (C)
TEMPERATURE (C)
SUPPLY CURRENT vs. DATA RATE
MAX9174 toc07
SUPPLY CURRENT vs. SUPPLY VOLTAGE
39 38 SUPPLY CURRENT (mA) 37 36 35 34 33 32 31 fIN = 155MHz
MAX9174 toc08
OUTPUT RISE/FALL TIME vs. SUPPLY VOLTAGE
290 280 RISE/FALL TIME (ps) 270 260 250 240 230 220 210 200 tF tR fIN = 155MHz
MAX9174 toc09
45 40 SUPPLY CURRENT (mA) 35 30 25 20 15 0
PRBS 223 - 1
40
300
30 100 200 300 400 500 600 700 800 DATA RATE (Mbps) 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
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670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters MAX9174/MAX9175
Typical Operating Characteristics (continued)
((MAX9174) VCC = +3.3V, |VID| = 0.15V, VCM = 1.25V, TA = +25C, RL = 100 1%, CL = 5pf, PD_ = VCC, unless otherwise noted.)
DIFFERENTIAL PROPAGATION DELAY vs. SUPPLY VOLTAGE
MAX9174 toc10
OUTPUT-TO-OUTPUT SKEW vs. SUPPLY VOLTAGE
MAX9174 toc11
DIFFERENTIAL OUTPUT VOLTAGE vs. LOAD RESISTANCE
DIFFERENTIAL OUTPUT VOLTAGE (mV)
MAX9174 toc12
3.0 DIFFERENTIAL PROPAGATION DELAY (ns) 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 3.0 3.1 3.2 3.3 3.4 3.5 tPLH tPHL fIN = 155MHz
10 9 OUTPUT-TO-OUTPUT SKEW (ps) 8 7 6 5 4 3 2 1 0 fIN = 155MHz
500 450 400 350 300 250 200
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
50 60 70 80 90 100 110 120 130 140 150 LOAD RESISTANCE ()
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
PROPAGATION DELAY vs. INPUT COMMON-MODE VOLTAGE
MAX9174 toc13a
PROPAGATION DELAY vs. INPUT COMMON-MODE VOLTAGE
2.9 PROPAGATION DELAY (ns) 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 tPLH tPHL fIN = 155MHz
MAX9174 toc13b MAX9174 toc14b
2.8 2.7 PROPAGATION DELAY (ns) 2.6 2.5 2.4 tPLH 2.3 2.2 0.075 tPHL
MAX9174 fIN = 155MHz
3.0
0.825
1.575
2.325
2.0 0.075 0.525 0.975 1.425 1.875 2.325 2.775 3.225 INPUT COMMON-MODE VOLTAGE (V)
INPUT COMMON-MODE VOLTAGE (V)
OUTPUT-TO-OUTPUT SKEW vs. INPUT COMMON-MODE VOLTAGE
MAX9174 toc14a
OUTPUT-TO-OUTPUT SKEW vs. INPUT COMMON-MODE VOLTAGE
6.0 5.5 OUTPUT-TO-OUTPUT SKEW (ps) 5.0 4.5 4.0 3.5 3.0 2.5 MAX9175 fIN = 155MHz
8.0 7.8 OUTPUT-TO-OUTPUT SKEW (ps) 7.6 7.4 7.2 7.0 6.8 6.6 6.4 6.2 6.0 0.075 0.825 1.575 MAX9174 fIN = 155MHz
2.325
2.0 0.075 0.525 0.975 1.425 1.875 2.325 2.775 3.225 INPUT COMMON-MODE VOLTAGE (V)
INPUT COMMON-MODE VOLTAGE (V)
6
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670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters
Pin Description
PIN MAX 1 2 3 4 5 6 7 8 9 10 -- QFN 1 2 3 4 5 6 7 8 9 10 EP IN+ INGND PD0 PD1 OUT0OUT0+ VCC OUT1OUT1+ Exposed Pad Noninverting Differential Input Inverting Differential Input Ground LVTTL/LVCMOS Input. OUT0+, OUT0- are high impedance to ground when PD0 is low. Internal pulldown resistor to GND. LVTTL/LVCMOS Input. OUT1+, OUT1- are high impedance to ground when PD1 is low. Internal pulldown resistor to GND. Inverting LVDS Output 0 Noninverting LVDS Output 0 Power Supply Inverting LVDS Output 1 Noninverting LVDS Output 1 Exposed Pad. Solder to ground. NAME FUNCTION
MAX9174/MAX9175
Detailed Description
The MAX9174/MAX9175 are 670MHz, low-jitter, lowskew 1:2 splitters ideal for protection switching, loopback, and clock and signal distribution. The devices feature ultra-low 80psP-P deterministic jitter (max) that ensures reliable operation in high-speed links that are highly sensitive to timing error. The MAX9174 has a fail-safe LVDS input and LVDS outputs. The MAX9175 has an anything differential input (CML/LVDS/LVPECL) and LVDS outputs. The outputs can be put into high impedance using the power-down inputs. The MAX9174 features a fail-safe circuit that drives the outputs high when the input is open, undriven and shorted, or undriven and terminated. The MAX9175 has a bias circuit that forces the outputs high when the input is open. The power-down inputs are compatible with standard LVTTL/LVCMOS logic. The power-down inputs tolerate undershoot of -1V and overshoot of VCC + 1V. The MAX9174/MAX9175 are available in 10-pin MAX and 10-lead thin QFN packages, and operate from a single +3.3V supply over the -40C to +85C temperature range.
A differential output voltage is produced by steering current through the parallel combination of the integrated differential output resistor and transmission line impedance/termination resistor. When driving a 100 termination resistor, a differential voltage of 250mV to 475mV is produced. For loads greater than 100, the output voltage is larger, and for loads less than 100, the output voltage is smaller. See the Differential Output Voltage vs. Load Resistance curve in Typical Operating Characteristics for more information. The outputs are short-circuit current limited for single-ended and differential shorts.
MAX9174 Input Fail-Safe
The fail-safe feature of the MAX9174 sets the outputs high when the differential input is: * Open * Undriven and shorted * Undriven and terminated Without a fail-safe circuit, when the input is undriven, noise at the input may switch the outputs and it may appear to the system that data is being sent. Open or undriven terminated input conditions can occur when a cable is disconnected or cut, or when a driver output is in high impedance. A shorted input can occur because of a cable failure.
Current-Mode LVDS Outputs
The LVDS outputs use a current-steering configuration. This approach results in less ground bounce and less output ringing, enhancing noise margin and system speed performance.
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670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters MAX9174/MAX9175
When the input is driven with a differential signal of |VID| = 50mV to 1.2V within a voltage range of 0 to 2.4V, the fail-safe circuit is not activated. If the input is open, undriven and shorted, or undriven and terminated, an internal resistor in the fail-safe circuit pulls the input above VCC - 0.3V, activating the fail-safe circuit and forcing the outputs high (Figure 1).
Table 1. Input Function Table
INPUT (IN+) - (IN-) +50mV -50mV -50mV < VID < +50mV MAX9175 MAX9174 Open Open, undriven short, or undriven parallel termination H OUTPUTS (OUT_+) - (OUT_-) H L Indeterminate
Overshoot and Undershoot Voltage Protection
The MAX9174/MAX9175 are designed to protect the power-down inputs (PD0 and PD1) against latchup due to transient overshoot and undershoot voltage. If the input voltage goes above VCC or below GND by up to 1V, an internal circuit limits input current to 1.5mA.
Table 2. Power-Down Function Table
PD1 H L or open L or open High PD0 H L or open High L or open OUT_+, OUT_Both outputs enabled Shutdown to minimum power, outputs high impedance to ground OUT0 enabled, OUT1 high impedance to ground OUT1 enabled, OUT0 high impedance to ground
Applications Information
Power-Supply Bypassing
Bypass the VCC pin with high-frequency surface-mount ceramic 0.1F and 0.001F capacitors in parallel as close to the device as possible, with the smaller valued capacitor closest to VCC.
Differential Traces
Input and output trace characteristics affect the performance of the MAX9174/MAX9175. Use controlledimpedance differential traces (100 typ). To reduce radiated noise and ensure that noise couples as common mode, route the differential input and output signals within a pair close together. Reduce skew by matching the electrical length of the two signal paths that make up the differential pair. Excessive skew can result in a degradation of magnetic field cancellation. Maintain a constant distance between the differential traces to avoid discontinuities in differential impedance. Minimize the number of vias to further prevent impedance discontinuities.
VCC RIN2
VCC RIN3 IN+ TO OUTPUT INRIN3
COMPARATOR
IN+ RIN1 VCC - 0.3V
RIN1 INDIFFERENTIAL RCVR MAX9174 INTERNAL FAIL-SAFE CIRCUIT MAX9175 INPUT
Cables and Connectors
Interconnect for LVDS typically has a controlled differential impedance of 100. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Avoid the use of unbalanced cables such as ribbon or simple coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver.
Figure 1. Input Structure
Termination
The MAX9174/MAX9175 require external input and output termination resistors. For LVDS, connect an input
termination resistor across the differential input and at the far end of the interconnect driven by the LVDS outputs. Place the input termination resistor as close to the receiver input as possible. Termination resistors should match the differential impedance of the transmission line. Use 1% surface-mount resistors.
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670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters MAX9174/MAX9175
OUT_+
5k
OUT_+ 1.25V 1.20V 1.25V 1.20V OUT_ IN+ INVOD RL
1.25V
VTEST = 0 TO VCC
IN+ IN-
RL/2
1.20V 1.25V 1.20V
VOS RL/2
5k
OUT_ -
Figure 2. VOD Test Circuit
Figure 3. VOS Test Circuit
OUT1+
5k
RL OUT15k CL CL VTEST = 0 TO VCC OUT0+ IN+ PULSE GENERATOR INOUT050 50 5k CL CL RL 5k
Figure 4. Transition Time, Propagation Delay, and Output-to-Output Skew Test Circuit
The MAX9174/MAX9175 feature an integrated differential output resistor. This resistor reduces jitter by damping reflections produced by a mismatch between the transmission line and termination resistor at the far end of the interconnect.
IEC 61000-4-2 Level 4 ESD Protection
The IEC 61000-4-2 standard (Figure 9) specifies ESD tolerance for electronic systems. The IEC 61000-4-2 model specifies a 150pF capacitor that is discharged into the device through a 330 resistor. The MAX9174/ MAX9175 differential inputs and outputs are rated for IEC 61000-4-2 level 4 (8kV Contact Discharge and 15kV Air-Gap Discharge). The Human Body Model (HBM, Figure 10) specifies a 100pF capacitor that is discharged into the device through a 1.5k resistor. IEC 61000-4-2 level 4 discharges higher peak current and more energy than the HBM due to the lower series resistance and larger capacitor.
9
Board Layout
Separate the differential and single-ended signals to reduce crosstalk. A four-layer printed circuit board with separate layers for power, ground, differential signals, and single-ended logic signals is recommended. Separate the differential signals from the logic signals with power and ground planes for best results.
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670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters MAX9174/MAX9175
IN-
IN+ tPLH OUT_tPHL
OUT_+ VOS = ((VOUT_+) + (VOUT_-))/2 80% VOD+ 0V (OUT_+) - (OUT_-) 20% tR tF 0V VOD80%
20%
Figure 5. Transition Time and Propagation Delay Timing
IN+
IN-
OUT0+
OUT0-
OUT1+
OUT1tSKOO tSKOO
Figure 6. Output-to-Output Skew
10
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670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters MAX9174/MAX9175
VCC + 1V VCC PD_ VCC/2 0 -1.0V tPD OUT_+ WHEN VID = +50mV OUT_- WHEN VID = -50mV 50% tPU VOH 50% 1.25V
OUT_+ WHEN VID = -50mV OUT_- WHEN VID = +50mV tPD
1.25V 50% 50% VOL tPU
Figure 7. Power-Up/Down Delay Waveform
MAX9174 MAX9175 1.25V 1.20V 1.25V 1.20V ININ+
OUT1+
RL/2
1.25V OUT1RL/2
OUT0+ RL/2
OUT0PULSE GENERATOR 50
RL/2
1.25V
Figure 8. Power-Up/Down Delay Test Circuit
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11
670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters MAX9174/MAX9175
RC 50 TO 100 CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE
RD 330 DISCHARGE RESISTANCE DEVICE UNDER TEST HIGHVOLTAGE DC SOURCE
RC 1M CHARGE-CURRENTLIMIT RESISTOR
RD 1.5k DISCHARGE RESISTANCE DEVICE UNDER TEST
Cs 150pF
STORAGE CAPACITOR
Cs 100pF
STORAGE CAPACITOR
Figure 9. IEC 61000-4-2 Contact Discharge ESD Test Model
Figure 10. Human Body ESD Test Model
Pin Configurations
TOP VIEW
MAX9174 MAX9175 IN+ DIFFERENTIAL RECEIVER IN-
Functional Diagram
OUT1+ LVDS DRIVER 0 OUT1-
IN+ 1 INGND PD0 PD1 2 3 4 5
10 OUT1+ 9 OUT1VCC OUT0+ OUT0-
IN+ 1 INGND PD0 PD1 2 3 4 5
10 OUT1+ 9 OUT1VCC OUT0+ OUT0-
MAX9174 MAX9175
8 7 6
MAX9174 MAX9175
EXPOSED PAD
8 7 6
MAX
OUT0+
THIN QFN (LEADS UNDER PACKAGE)
LVDS DRIVER 1 OUT0PD0 PD1
Chip Information
TRANSISTOR COUNT: 693 PROCESS: CMOS
12
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670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
10LUMAX.EPS
MAX9174/MAX9175
e
10
4X S
10
INCHES MAX DIM MIN A 0.043 A1 0.002 0.006 A2 0.030 0.037 D1 0.116 0.120 D2 0.114 0.118 E1 0.116 0.120 0.118 E2 0.114 0.199 H 0.187 L 0.0157 0.0275 L1 0.037 REF b 0.007 0.0106 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S 0 6
MILLIMETERS MAX MIN 1.10 0.15 0.05 0.75 0.95 3.05 2.95 3.00 2.89 3.05 2.95 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.177 0.270 0.500 BSC 0.090 0.200 0.498 REF 0 6
H y 0.500.1 0.60.1
1
1
0.60.1
TOP VIEW
BOTTOM VIEW
D2 GAGE PLANE A2 A b A1 D1
E2
c
E1 L1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0061
1 1
I
______________________________________________________________________________________
13
670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters MAX9174/MAX9175
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
6, 8, &10L, QFN THIN.EPS
1 2
L D A A2
PIN 1 ID
D2
1
N
1
b
PIN 1 INDEX AREA
C0.35 [(N/2)-1] x e REF. e
E
DETAIL A
E2
A1
k
C L
C L
L e A e
L
SEMICONDUCTOR
PROPRIETARY INFORMATION TITLE:
DALLAS
PACKAGE OUTLINE, 6, 8 & 10L, TDFN, EXPOSED PAD, 3x3x0.80 mm
NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY
APPROVAL DOCUMENT CONTROL NO. REV.
21-0137
D
COMMON DIMENSIONS SYMBOL A D E A1 L k A2 MIN. 0.70 2.90 2.90 0.00 0.20 MAX. 0.80 3.10 3.10 0.05 0.40
0.25 MIN. 0.20 REF.
PACKAGE VARIATIONS PKG. CODE T633-1 T833-1 T1033-1 N 6 8 10 D2 1.500.10 1.500.10 1.500.10 E2 2.300.10 2.300.10 2.300.10 e 0.95 BSC 0.65 BSC 0.50 BSC JEDEC SPEC MO229 / WEEA MO229 / WEEC MO229 / WEED-3 b 0.400.05 0.300.05 0.250.05 [(N/2)-1] x e 1.90 REF 1.95 REF 2.00 REF
SEMICONDUCTOR
PROPRIETARY INFORMATION TITLE:
DALLAS
PACKAGE OUTLINE, 6, 8 & 10L, TDFN, EXPOSED PAD, 3x3x0.80 mm
APPROVAL DOCUMENT CONTROL NO. REV.
2 2
21-0137
D
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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